can define set of gate primitives by designing and specifying new
primitive elements called user-defined primitives (UDPs). Instances of
these new UDPs can then be used in exactly the same manner as the gate
primitives to represent the circuit being modeled.
Defined Primitives can describe both combinational (Example
1) and sequential (Example 2)
circuits. The behavioral description is provided as a truth table.
can have only one output.
Inout ports are illegal.
Combinational UDP should not have more than 10 inputs.
Sequential UDP should not have more than 9 inputs.
Vector declaration for UDP ports is illegal.
UDP declaration starts with the keyword
primitive and ends with the keyword
endprimitive. A port list, an output port declaration and input
ports declaration are similar to their equivalents in a module
port list contains a comma-separated list of primitive ports. There can be
only one output port and several input ports. The inout ports are illegal.
The first port on the list should be the output port. There are some
restrictions concerning the number of input ports. The combinational UDPs
list of ports should not contain more than 10 inputs, and the sequential
UDPs port list should not contain more than 9 inputs. If the port list
contains more inputs, then a warning will be issued. These restrictions
are caused by illegibility of written UDPs.
and output port declarations should match the port list of the UDP they
are enclosed in. If the described UDP is sequential, then reg declaration
for output port should be provided. All ports of the UDP should be of
scalar type (1-bit wide). Vectors are illegal.
Sequential UDPs can contain an initial statement for an output port. This
statement begins with the keyword initial,
followed by an assignment to the output port. Assigned values should be
1-bit wide and there must not be any delays.
state table starts with the keyword table
and ends with the keyword endtable.
The state tables for combinational and sequential UDPs are different. The
state table is comprised of rows each of which ended with a the semicolon.
Table row describes the behavior of UDP for a particular combination of
inputs. The combinational UDPs have two fields separated by a colon. One
field is for the inputs and one for the outputs. The sequential UDPs have
three fields: one for the inputs, one for the current output state, and
one for the next output state. If any combination of input signals, is not
explicitly specified in the UDP declaration, the output value will be
unknown (x). A particular combination of inputs can be specified only one
Verilog: Table of Contents
Ch: 1. 2.
11. 12. 13.
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