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Verilog Tutorial: Harsha Perla

Verilog Data types

 

Data types in Verilog are divided in to nets and registers.  wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1 and trireg are net data types. reg, integer, time and real are register data types.

Net Data Types

wire is the most widely used net data type. It represents 1 bit interconnecting wire. If you use a signal to connect two modules in verilog code without declaring, it will be considered as wire by default. You can also declare a wire using syntax
wire identifier;

 The net types wire and tri shall be identical in their syntax and functions; two names are provided so that the name of a net can indicate the purpose of the net in that model. A wire net can be used for nets that are driven by a single gate or continuous assignment. The tri net type can be used where multiple drivers drive a net.

wor and trior are wired OR and multiple driver OR respectively. That means, logical OR of all the signals assigned to a wor type of signal will be the effective  value of that signal. Consider the following example:

module wortest();

wor w1, w2, w3, w4;

assign w1 = 0;
assign w1 = 0;

assign w2 = 0;
assign w2 = 1;

assign w3 = 1;
assign w3 = 0;

assign w4 = 1;
assign w4 = 1;

initial
begin
    $display(w1, w2, w3, w4);
end

endmodule

Output of this code will be

0 1 1 1

Similarly wand and triand are wired AND and multiple driver AND respectively. Logical AND of all the signals assigned to a wand type of signal will be the effective value of it.

tri0 and tri1 will be pulled down or pulled up when not driven. That is, if you do not connect a tri0 type of signal or assigned high impedance value to it, value will be 0 instead of z.

In the following code, you can make out the difference between wire, tri0 and tri1.

 

module tritest();

wire w1, w2, w3, w4;
tri0 t01, t02, t03, t04;
tri1 t11, t12, t13, t14;

assign w1 = 0;
assign t01 = 0;
assign t11 = 0;

assign w2 = 1'bz;
assign t02 = 1'bz;
assign t12 = 1'bz;

assign w3 = 1;
assign t03 = 1;
assign t13 = 1;

initial
begin
  #1;
  $display(w1, w2, w3, w4);
  $display(t01, t02, t03, t04);
  $display(t11, t12, t13, t14);

end
endmodule

and the output will be as follows:

0z1z
0010
0111

supply0 and supply1 are tied to logic 0 and 1 respectively.

Register Data Types

reg is a single bit register data type. If a value is assigned to reg type of signal, value will retain until a new value is assigned. In verilog, a register data type need not represent a real hardware register. So, it need not be consisting of  a flip-flop. It just means that a signal that holds the value. Default value of an un-initialized reg is 'x' or undefined.

integer, time and real are other register type of datatypes. integer is a signed variable of 32 bits, time is unsigned integer, 64 bits and real is double precision floating point variable.
 

Prev. : Identifiers and Keywords
Verilog: Table of Contents
Ch:  1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
Next: Verilog Operators

 

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