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Verilog Tutorial: Harsha Perla

Verilog Primitives

 

Verilog Provides in-built primitives for basic gate and switch level modeling. Any circuit can be modeled by using continuous assignment of gate and switch level primitives.

and (strong1, weak0)#(1,2) gate1(out, in1, in2);

This is an and gate with output 'out' and two inputs in1 and in2. Strong1 and weak0 are optional driving strengths and gate1 is optional instance name that can be used while debugging. First parameter in the  bracket is output and you can have any number of inputs after that. This is how you use a 3 input and gate without instance name, delay and driving strengths:

and (out, in1, in2, in3);

and, nand, not, nor, or, xor, xnor, buf, bufif0, bufif1, rtranif1, nmos, pmos, rpmos, tran, rtran, pullup, pulldown, cmos, rnmos, tranif1, tranif0, notif0, notif1, rtranif0, rcmos are the built-in primitives.

Following table provides truth table of and, or, nor, xor, nand and xnor gates. These gates can have one output and one or more inputs.

Basic Gates

and

0

1

x

z

 

or

0

1

x

z

 

xor

0

1

x

z

0

0

0

0

0

 

0

0

1

x

x

 

0

0

1

x

x

1

0

1

x

x

 

1

1

1

1

1

 

1

1

0

x

x

x

0

x

x

x

 

x

x

1

x

x

 

x

x

x

x

x

z

0

x

x

x

 

z

x

1

x

x

 

z

x

x

x

x

nand

0

1

x

z

 

nor

0

1

x

z

 

xnor

0

1

x

z

0

1

1

1

1

 

0

1

0

x

x

 

0

1

0

x

x

1

1

0

x

x

 

1

0

0

0

0

 

1

0

1

x

x

x

1

x

x

x

 

x

x

0

x

x

 

x

x

x

x

x

z

1

x

x

x

 

z

x

0

x

x

 

z

x

x

x

x

Here is the truth table for buf and not gate. These can have one input and one or more output. last parameter in the port list is the input.

 

buf

 

not

input

output

 

input

output

0

0

 

0

1

1

1

 

1

0

x

x

 

x

x

z

x

 

z

x

 

bufif1, bufif0, notif1, notif0 Gates

These gates have three ports: the first is an output port, the second is a data port, and the third is a control port. The control port is used to set gates in high-impedance state.

bufif0

control input

 

bufif1

control input

 

0

1

x

z

   

0

1

x

z

data

0

0

z

L

L

 

data

0

z

0

L

L

input

1

1

z

H

H

 

input

1

z

1

H

H

 

x

x

z

x

x

   

x

z

x

x

x

 

z

x

z

x

x

   

z

z

x

x

x

notif0

control input

 

notif1

control input

 

0

1

x

z

   

0

1

x

z

data

0

1

z

H

H

 

data

0

z

1

H

H

input

1

0

z

L

L

 

input

1

z

0

L

L

 

x

x

z

x

x

   

x

z

x

x

x

 

z

x

z

x

x

   

z

z

x

x

x

The L and H symbols have a special meaning. The L symbol means that the output has 0 or z value. The H symbol means that the output has 1 or z value. Any transition to H or L is treated as a transition to x.

nmos, pmos, rnmos, rpmos, cmos, and rcmos switches

The nmos switch is used to model N-type MOS (Metal-Oxide Semiconductor) transistor and the pmos switch is used to model P-type MOS (Metal-Oxide Semiconductor) transistor. The rnmos switch is used to model resistive nmos transistor and the rpmos switch is used to model resistive pmos transistor. The cmos switch should be treated as combination of a pmos switch and an nmos switch, which have common data input and data output. The rcmos switch should be treated as combination of an rpmos switch and an rnmos switch, which have common data input and data output.

The instantiation of these MOS switches can contain zero, one, two, or three delays.

The strength declaration is illegal. The nmos, pmos and cmos switches reduce supply strength of the signals to strong strength. Signals with others strengths are passed from input to output without a strength reduction. The rnmos, rpmos and rcmos switches reduce supply and strong strength of signals to pull strength. The pull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction.

The nmos, pmos, rnmos, rpmos switches have three ports: the first is an output port, the second is a data port, and the third is a control port.

The cmos and rcmos switches have four ports: the first is an output port, the second is a data port, the third is a n-control port, and the fourth a is p-control port.

pmos

control input

 

nmos

control input

rpmos

0

1

x

z

 

rnmos

0

1

x

Z

data

0

0

z

L

L

 

data

0

z

0

L

L

input

1

1

z

H

H

 

input

1

z

1

H

H

 

x

x

z

x

x

   

x

z

x

x

x

 

z

z

z

z

z

   

z

z

z

z

z

cmos

N control

rcmos

0

1

x

z

 

P control

 

0

1

x

z

0

1

x

z

0

1

x

z

0

1

x

z

Data

0

0

z

L

L

0

0

0

0

0

L

L

L

0

L

L

L

 

1

1

z

H

H

1

1

1

1

1

H

H

H

1

H

H

H

 

x

x

z

x

x

x

x

x

x

x

x

x

x

x

x

x

x

 

z

z

z

z

z

z

z

z

z

z

z

z

z

z

z

z

z

Symbols L and H have a special meaning. The symbol L means that the output has 0 or z value. The symbol H means that the output has 1 or z value. Any transition to H or L is treated as a transition to x.

rtranif0, rtranif1, tranif0 and tranif1 switches

The instantiation of these bi-directional pass switches can contain zero, one, two, or three delays.

The strength declaration is illegal. The tranif0 and tranif1 switches reduce supply strength of signals to strong. Signals with others strengths are passed from input to output without strength reduction. The rtranif0 and rtranif1 switches reduce supply and strong strength of signals to pull. The pull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction.

The rtranif0, rtranif1, tranif0 and tranif1 switches have three ports: two bidirectional data ports and one control port (third position on port list).

tran and rtran switches

The instance of these bidirectional switches cannot contain delay and strength declaration.

The tran switches reduce supply strength of signals to strong strength. Signals with others strengths are passed from input to output without strength reduction. The rtran switches reduce supply and strong strength of signals to pull. The pull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction.

The tran and rtran switches have two bidirectional data ports.

pullup and pulldown sources

The instantiation pullup and pulldown sources cannot contain delay declaration. The pullup can contain only strength1 specification (the strength0 declaration is optional). The pulldown can contain only strength0 specification (the strength1 declaration is optional).

The pullup source places a logic value 1 on connected signals. The pull down source places a logic value 0 on connected signals.

Next part explains about user defined primitives

Prev. : Overview of Verilog
Verilog: Table of Contents
Ch:  1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
Next: User defined Primitives

 

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