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Verilog Tutorial: Harsha Perla

Identifiers and Keywords

 

White Space and Comments

White space is defined as any of the following characters: blanks, tabs, newlines, and formfeeds. These are ignored except for when they are found in strings.

There are two forms of comments. The single line comment begins with the two characters
// and ends with a new-line.
A block comment begins with the two characters /* and ends with the two characters */. Block comments may span several lines. However, they may not be nested.

Identifiers

Identifiers are names that are given to elements such as modules, registers, ports, wires, instances, and procedural blocks. An identifier is any sequence of letters, digits, and the underscore (_) symbol except that:
the first character must not be a digit, and the identifier must be 1024 characters or less.

Verilog is case sensitive, ie Upper and lower case letters are considered to be different. System tasks and system functions are identifiers that always start with the dollar symbol. Escaped identifiers allow for any printable ASCII character to be included in the name. Escaped identifiers begin with white space. The backslash (\) character leads off the identifier, which is then terminated with white space. The leading backslash character is not considered part of the identifier.

Examples of escaped identifiers include:

 \flip-flop
 \a+b

Escaped identifiers are used for translators from other CAD systems. These systems may allow special characters in identifiers. Escaped identifiers should not be used under normal circumstances.

Verilog Keywords

always
and
assign
attribute
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endattribute
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1
if
ifnone
initial
inout
input
integer
join
medium
module
large
macromodule
nand
negedge
nmos
nor
not
notif0
notif1
or
output
parameter
pmos
posedge
primitive
pull0
pull1
pulldown
pullup
rcmos
real
realtime
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
signed
small
specify
specparam
strength
strong0
strong1
supply0
supply1
table
task
time
tran
tranif0
tranif1
tri
tri0
tri1
triand
trior
trireg
unsigned
vectored
wait
wand
weak0
weak1
while
wire
wor
xnor
xor

 

Prev. : User Defined Primitives
Verilog: Table of Contents
Ch:  1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
Next: Verilog datatypes

 

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