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SystemVerilog Tutorial PART III: by Abhiram Rao

 Structures & Unions in SystemVerilog

 

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Structures:

 

User can create a logical collection of objects using struct

  • Not restricted to elements of same size and type as with arrays

  • Can be referenced as a whole or by individual element

 

 

typedef enum {R[31]} reg_t;
typedef
enum {NOP, LD, ST, BR, ADD, SUB, NEG, AND, OR, NOT, SHR, SHL, STOP} opc_t;
struct packed {
        opc_t       opcode;
        reg_t       ra, rb, rc;
        logic[11:0] c3;
} IR;

always_ff @(posedge clk, negedge rstn)
      if (~rstn)
          IR <= '0;
      else
          IR <= dpb;

assign OpC = IR.opcode;

 

Unions:  

 Unions also allow the user to create a collection of objects

  • However, unions only store a single element

  • Advantage: single element stored with different representations

typedef struct packed {

    opc_t       opcode;

    reg_t       ra, rb, rc;

    logic [11:0] c3;

} instr_format_3;

 

typedef struct packed {

    opc_t       opcode;

    reg_t       ra, rb;

    logic [16:0] c2;

} instr_format_2;

 

typedef struct packed {

    opc_t       opcode;

    reg_t       ra;

    logic [21:0] c1;

} instr_format_1;

 

typedef union packed {

    instr_format_1 IW1;

    instr_format_2 IW2;

    instr_format_3 IW3;

    logic [31:0] BITS;

} InstrType;

 

InstrType IR;

 

always_comb

 if (c1o)

   q = {{10{IR.IW1.c1[21]}}, IR.IW1.c1};

 else if (c2o)

   q = {{15{IR.IW2.c2[16]}}, IR.IW2.c2};

 else

   q = IR.BITS;
 

 

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