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Sudhish Kumar |
Email: [email protected]
[email protected]
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OBJECTIVE: |
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To make maximum
possible use of my educational background, development experience,
problem solving abilities and programming skills which can benefit the
company�s core goals. |
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Current Status: |
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Working as Member
technical staff -VLSI in Kacper
Technologies Pvt. Ltd.; Bangalore. |
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EDUCATIONAL QUALIFICATION: |
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BE in
Information Science
2005, N.M.A.M.I.T., Nitte.
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TECHNICAL PROFICIENCY: |
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Programming
languages:
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C, C ++, Visual C++, Visual Basic, Java, J2EE |
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Hardware Design and
Verification languages
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Verilog, SystemVerilog |
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Machine level
programming Languages:
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8086, 8085 |
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Operating Systems
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Microsoft Windows, RedHat
Linux |
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Hardware Tools |
MentorGraphics QuestaSim,
ModelSim, Xilinx Project Navigator, Aldec Riveara, ActiveHDL, Simucad
Silos, iVerilog |
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Other Tools and Packages:
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MS-office, HT
Soft Hi-Tide, Visual Studio, Photo impact, Flash,
GIF animators, Web designing tools. |
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Hardware proficiency:
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VLSI, Digital design,
Digital Communication. |
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Domain Knowledge: |
SONET/ SDH, CAN. |
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INTERESTS: |
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�
VLSI (ASIC and FPGA)
� Embedded
Systems
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Electronic Communication
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System Software
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Web designing
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Digital Signal
Processing |
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PROJECTS
UNDERTAKEN |
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1. ACADEMIC
PROJECT |
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TEAM SIZE:4
ROLE :
Responsible for designing and implementing atoms module, which
includes identifying atoms for every atom and identifying the
surface atoms by finding the hydrophilic atoms. |
TITLE: �Molecular
Docking Applications� |
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PROJECT
PROFILE:
Molecular docking System is a Standalone Embedded application. This
application helps the chemical scientists in fetching the samples of
different atoms and studies the molecular structures of atoms.
The binding site and the bound conformation of the two molecules are
to be calculated. Development of docking techniques involved two
stages:
�
Identify Surface Representation: efficiently represent the docking
surface and regions of interests.
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Surface Matching: match corresponding surfaces to optimize binding
store.
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2. ACADEMIC
PROJECT |
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TEAM SIZE:1
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TITLE:
�
WAP Based E-Mail Gateway
� |
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PROJECT
PROFILE:
Email accesses from mobile phones are enabled by this project. It
acts as a gateway to connect mailing access from any WAP device.
Particularly mobile phones use them in large scale. Designed a
mobile shaped interface using WML and back-end using Servlets.
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Maintain a detailed list of all the users with their personal
details like address, phone numbers etc.
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Add a new user to the list, option to change an existing users
password.
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This gives access to checking mails, sending and receiving mails
from mobile itself.
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Option of a user signing up.
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Maintain a database where u can store many kinds of pictures, which
will be used by the user to send any picture messages. |
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3.
Sonet/SDH Verification |
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Development
SONET/SDH SystemVerilog Verification IP
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Currently working on development of
verification environment for SONET/SDH SV-IP. Task includes
developing SONET/SDH SV-IP, which is used in the environment as
reference SONET/SDH model, data & Temporal checkers, scoreboard and
monitors.
The SV-IP, checkers, scoreboard and monitors are developed using
�System Verilog�
� SONET/SDH SV-IP � Models the general SONET/SDH device
specification by the GR253CORE.003.
� Monitor � It acts as a SONET/SDH passive node (Receiver) in
system.
� Output checkers � These are re-active checkers. Whenever any
output changes, these checkers will be triggered.
Scoreboard � Main test model which checks for the correct
transmission/reception of messages and the procedures involved.
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4.Can Protocol Verification |
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Implementation of verification
environment for CAN Protocol
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Developed a verification environment
for CAN protocol using SystemVerilog. Verification component is
composed by a configurable number of CAN agents, able to generate
and inject frames or respond to frame requests according to CAN
specification. It includes a monitor that logs all traffic
information and collects items for test functional coverage. The
embedded protocol checker is a runtime tool checking CAN rules of
the current bus traffic and the checker prompts the user about the
errors.
Responsible for implementation of Scoreboard.
� Main test model which checks for the correct transmission /
reception of messages and the procedures involved.
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PERSONAL
PROFILE |
If you want to contact me, use this form.
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Name
: ABHIRAM RAO
Father�s
Name :
DR.D.SHRIPATHI RAO
Date of Birth : 22-10-1983
Nationality : Indian
Religion : Hindu
Mother Tongue : Tulu
Sex : Male
Marital Status : Single
Languages Known : English, Kannada, Hindi |
