SystemVerilog Tutorial PART II: by Abhiram Rao

SystemVerilog Operators

<Previous    Page       Next>

•  System verilog adds the following operators ++ and – increment and decrement operators similar to C

•  Loop variables can be declared inside a loop. In verilog, the variable has to be declared and  then used within a loop

 Operator Type Operator Symbol Operation Performed Arithmetic * Multiply / Division + Add - Subtract % Modulus + Unary plus - Unary minus Logical ! Logical negation && Logical and || Logical or Relational > Greater than < Less than >= Greater than or equal <= Less than or equal Equality == Equality != inequality Reduction ~ Bitwise negation ~& nand | or ~| nor ^ xor ^~ xnor ~^ xnor Shift >> Right shift << Left shift Concatenation { } Concatenation Conditional ? conditional

 Assignment operator =, +=, -=,  *= ,  /=,  %=,  &=, |=, ^=,  <<=, >>=, <<<=, >>>= Conditional_Expression cond_predicate ? { attribute_instance } expression : expression Unary_operator +, -, !, ~, &, ~&, |,  ~|,  ^, ~^, ^~ Binary_operator +,-, *, /, %, ==, !=, ===,!==, =?=, !?=, &&, ||, ** <, >, <=, >=, &, |, ^, ~^, ^~, >>, <<, <<<, >>> Increment, decrement operators ++, -- Unary_module_path_operator !, ~, &, ~&, |, ~|, ^, ~^, ^~ Binary_module_path_operator ==, !=, &&, ||, &, |, ^, ~^, ^~

Concatenation

Braces ( { } ) are used to show concatenation, as in Verilog. The concatenation is treated as a packed vector of bits. It can be used on the left hand side of an assignment or in an expression.

 logic log1, log2, log3; {log1, log2, log3} = 3’b111; {log1, log2, log3} = {1’b1, 1’b1, 1’b1}; // same effect as 3’b111

SystemVerilog enhances the concatenation operation to allow concatenation of variables of type string. In general, if any of the operands is of type string, the concatenation is treated as a string, and all other arguments are implicitly converted to the string type. String concatenation is not allowed on the left hand side of an assignment, only as an expression.

 string sv = "SystemVerilog"; string s; s = {sv, " ", "is easy"}; \$display ("%s\n", s);        // displays 'SystemVerilog is easy' s = {s, ", enjoy"}; \$display ("%s\n", s);        // displays 'SystemVerilog is easy, enjoy’

<Previous    Page       Next>