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System
verilog adds the following operators ++ and � increment and decrement
operators similar to C
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Loop variables can be declared inside a loop. In verilog, the variable
has to be declared and then used within a loop
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Operator Type |
Operator Symbol |
Operation Performed |
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Arithmetic
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* |
Multiply |
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/ |
Division |
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+ |
Add |
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- |
Subtract |
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% |
Modulus |
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+ |
Unary plus |
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- |
Unary minus |
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Logical
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! |
Logical negation |
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&& |
Logical and |
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|| |
Logical or |
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Relational
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> |
Greater than |
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< |
Less than |
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>= |
Greater than or equal |
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<= |
Less than or equal |
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Equality
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== |
Equality |
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!= |
inequality |
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Reduction
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~ |
Bitwise negation |
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~& |
nand |
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| |
or |
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~| |
nor |
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^ |
xor |
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^~ |
xnor |
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~^ |
xnor |
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Shift
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>> |
Right shift |
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<< |
Left shift |
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Concatenation |
{ } |
Concatenation |
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Conditional |
? |
conditional |
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Assignment operator |
=,
+=, -=,
*=
, /=,
%=,
&=,
|=,
^=,
<<=,
>>=,
<<<=,
>>>=
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Conditional_Expression |
cond_predicate
?
{ attribute_instance } expression
:
expression |
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Unary_operator |
+,
-, !, ~, &, ~&, |, ~|, ^, ~^, ^~ |
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Binary_operator |
+,-, *, /, %, ==, !=, ===,!==, =?=, !?=, &&, ||, **
<,
>, <=, >=, &, |, ^, ~^, ^~, >>, <<, <<<, >>> |
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Increment, decrement operators |
++, -- |
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Unary_module_path_operator |
!,
~, &, ~&, |, ~|, ^, ~^, ^~ |
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Binary_module_path_operator |
==, !=, &&, ||, &, |, ^, ~^, ^~ |
Concatenation
Braces ( { } ) are
used to show concatenation, as in Verilog. The concatenation is treated as
a packed vector of bits. It can be used on the left hand side of an
assignment or in an expression.
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logic
log1, log2, log3;
{log1, log2, log3} =
3�b111;
{log1, log2, log3} =
{1�b1, 1�b1, 1�b1}; // same effect as 3�b111
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SystemVerilog
enhances the concatenation operation to allow concatenation of variables
of type string. In general, if any of the operands is of type
string,
the concatenation is treated as a string, and all other arguments are
implicitly converted to the
string
type. String
concatenation is not allowed on the left hand side of an assignment, only
as an expression.
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string
sv = "SystemVerilog";
string
s;
s = {sv, " ", "is
easy"};
$display ("%s\n", s);
// displays
'SystemVerilog is easy'
s = {s, ", enjoy"};
$display ("%s\n", s);
// displays 'SystemVerilog is easy, enjoy�
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