module fifo (
input clk,
input rstp,
input packet_t din,
input readp,
input writep,
output packet_t dout,
output logic emptyp,
output logic fullp
);

int i;

parameter DEPTH = 2, // 2 bits, e.g. 4 words in the FIFO.
MAX_COUNT = (1<<DEPTH); // topmost address in FIFO.

reg [(DEPTH-1):0] tail;
reg [(DEPTH-1):0] head;

reg [(DEPTH):0] count;

packet_t fifomem[0:MAX_COUNT];


always @(posedge clk) begin
if (rstp == 1) begin
dout <= {default:0};
end
else begin
dout <= fifomem[tail];
end
end

// Update FIFO memory.
always @(posedge clk)
if (rstp == 1'b0) begin
if (writep == 1'b1 && fullp == 1'b0)
fifomem[head] <= din;
end
else
fifomem={default:0};

// Update the head register.

always @(posedge clk) begin
if (rstp == 1'b1) begin
head <= 0;
end
else begin
if (writep == 1'b1 && fullp == 1'b0) begin
// WRITE
head <= head + 1;
end
end
end

// Update the tail register.

always @(posedge clk) begin
if (rstp == 1'b1) begin
tail <= 0;
end
else begin
if (readp == 1'b1 && emptyp == 1'b0) begin
// READ
tail <= tail + 1;
end
end
end

// Update the count register.

always @(posedge clk) begin
if (rstp == 1'b1) begin
count <= 0;
end
else begin
case ({readp, writep})
2'b00: count <= count;
2'b01:
// WRITE
if (!fullp)
count <= count + 1;
2'b10:
// READ
if (!emptyp)
count <= count - 1;
2'b11:
// Concurrent read and write.. no change in count
count <= count;
endcase
end
end

always @(count) begin
if (count == 0)
emptyp = 1'b1;
else
emptyp = 1'b0;
end

always @(count) begin
if (count < MAX_COUNT)
fullp = 1'b0;
else
fullp = 1'b1;
end

endmodule