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SystemVerilog Tutorial PART 28: by Abhiram Rao

Procedural Statements and Control Flow - Part 2


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Selection statements

conditional_statement ::=
                    [ unique_priority ] if ( expression ) statement_or_null [ else statement_or_null ]
            | if_else_if_statement
    if_else_if_statement ::=
                   [ unique_priority ] if ( expression ) statement_or_null
                   { else [ unique_priority ] if ( expression ) statement_or_null }
                   [ else statement_or_null ]
    case_statement ::= //
                   [ unique_priority ] case ( expression ) case_item { case_item } endcase
                 | [ unique_priority ] casez ( expression ) case_item { case_item } endcase
                 | [ unique_priority ] casex ( expression ) case_item { case_item } endcase
   case_item ::=
                  expression { , expression } : statement_or_null
                | default [ : ] statement_or_null
   unique_priority ::= unique | priority

In Verilog, an if (expression) is evaluated as a boolean, so that if the result of the expression is 0 or X, the
test is considered false.

SystemVerilog adds the keywords unique and priority, which can be used before an if. If either keyword
is used, it shall be a run-time warning for no condition to match unless there is an explicit else.

For example:
unique if((a==0) || (a==1)) $display("0 or 1");
else if (a == 2) $display("2");
else if (a == 4) $display("4");
// values 3,5,6,7 will cause a warning

priority if(a[2:1]==0) $display("0 or 1");
else if (a[2] == 0) $display("2 or 3");
else $display("4 to 7");
//covers all other possible values, so no warning

A unique if indicates that there should not be any overlap in a series of if...else...if conditions, allowing
the expressions to be evaluated in parallel. A software tool shall issue an error if it determines that there is a
potential overlap in the conditions.

A priority if indicates that a series of if...else...if conditions shall be evaluated in the order listed. In
the preceding example, if the variable �a� had a value of 0, it would satisfy both the first and second conditions,
requiring priority logic.

In Verilog, there are three types of case statements, introduced by case, casez and casex. With SystemVerilog,
each of these can be qualified by priority or unique. A priority case shall act on the first match
only. A unique case shall guarantee no overlapping case values, allowing the case items to be evaluated in
parallel. If the case is qualified as priority or unique, the simulator shall issue a warning message if an
unexpected case value is found. By specifying unique or priority, it is not necessary to code a default
case to trap unexpected case values. For example:

bit[2:0] a;
unique case(a) // values 3,5,6,7 will cause a run-time warning
0,1: $display("0 or 1");
2: $display("2");
4: $display("4");

priority casez(a)
2�b00?: $display("0 or 1");
2�b0??: $display("2 or 3");
default: $display("4 to 7");

The unique and priority keywords shall determine the simulation behavior. It is recommended that synthesis
follow simulation behavior where possible. Attributes may also be used to determine synthesis behavior.


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