SystemVerilog Assertions: ElectroSofts.com

SystemVerilog Tutorial PART 20: by Abhiram Rao

Assertions in SystemVerilog - Part 3

The following table summarizes some of the operations that can be performed on sequences.

Operation	Syntax	Explanation
Concatenation	seq1 ##1 seq2	seq2 begins on the clock after seq1 completes
Overlap	seq1 ##0 seq2	seq2 begins on the same clock on which seq1 completes
Ended Detection	seq1 ##1 seq2.ended	seq2 completes on the clock after seq1 completes, regardless of when seq2 started.
Repetition	seq1[*n:m]	Repeat seq1 a minimum of n and maximum of m times. May result in multiple matching sequences
First Match Detection	first_match(seq1)	If seq1 has multiple matches, use the first and ignore the rest
Or	seq1 or seq2	Compound sequence that matches when either seq1 or seq2 matches
And	seq1 and seq2	Matches when one sequence matches on or after the other sequence also matches
Length-matching And	seq1 intersect seq2	Matches on cycles at which both seq1 and seq2 match
Condition Qualification	cond throughout seq	cond is true for every cycle of seq
Within	seq1 within seq2	seq1 starts on or after seq2 and ends on or before the end of seq2

Declaring sequences

A sequence can be declared in

a module
an interface
a program
a clocking block
a package
a compilation-unit scope

Sequences are declared using the following syntax.:

concurrent_assertion_item_declaration ::=

...

sequence_declaration

sequence_declaration ::=

sequence sequence_identifier [ ( [ list_of_formals ] ) ] ;

{ assertion_variable_declaration }

sequence_expr ;

endsequence [ : sequence_identifier ]

sequence_instance ::=

ps_sequence_identifier [ ( [ actual_arg_list ] ) ]

actual_arg_list ::=

actual_arg_expr { , actual_arg_expr }

. formal_identifier ( actual_arg_expr ) { , . formal_identifier ( actual_arg_expr ) }

actual_arg_expr ::=

event_expression

data_type list_of_variable_identifiers ;

The clocking_event specifies the clock for the sequence. A sequence is declared with optional formal arguments. When a sequence is instantiated, actual arguments can be passed to the sequence. The sequence gets expanded with the actual arguments by replacing the formal arguments with the actual arguments. Semantic checks are performed to ensure that the expanded sequence with the actual arguments is legal.

An actual argument can replace an:

ï¿½ identifier

ï¿½ expression

ï¿½ event control expression

ï¿½ upper range as $

Note that variables used in a sequence that are not formal arguments to the sequence are resolved according to the scoping rules from the scope in which the sequence is declared.

sequence s1;

         @(posedge clk) a ##1 b ##1 c;

endsequence

sequence s2;

         @(posedge clk) d ##1 e ##1 f;

endsequence

sequence s3;

        @(negedge clk) g ##1 h ##1 i;

endsequence

In this example, sequences s1 and s2 are evaluated on successive posedge events of clk. The sequence s3 is evaluated on successive negedge events of clk.

Another example of sequence declaration, which includes arguments is shown below:

sequence s20_1(data,en);

(!frame && (data==data_bus)) ##1 (c_be[0:3] == en);

endsequence

Sequence s20_1 does not specify a clock. In this case, a clock would be inherited from some external source, such as a property or an assert statement. A sequence can be referred to by its name. A hierarchical name can be used, consistent with the SystemVerilog naming conventions. A sequence can be referenced in a property, an assert statement, or a cover statement.

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