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Sudhish Kumar

 


Email: sudhish@electrosofts.com
            abhiramrao@gmail.com

OBJECTIVE:
To make maximum possible use of my educational background, development experience, problem solving abilities and programming skills which can benefit the company’s core goals.
Current Status:
Working as Member technical staff -VLSI in Kacper Technologies Pvt. Ltd.; Bangalore.
EDUCATIONAL QUALIFICATION:

BE in Information Science 2005, N.M.A.M.I.T., Nitte.

TECHNICAL PROFICIENCY:

Programming languages:                       

C, C ++, Visual C++, Visual Basic, Java, J2EE
Hardware Design and Verification languages Verilog, SystemVerilog

Machine level programming Languages:

8086, 8085
Operating Systems Microsoft Windows, RedHat Linux
Hardware Tools

MentorGraphics QuestaSim, ModelSim, Xilinx Project Navigator, Aldec Riveara, ActiveHDL, Simucad Silos, iVerilog

Other Tools and Packages:

 MS-office, HT Soft Hi-Tide, Visual Studio,  Photo impact, Flash, GIF animators, Web designing tools.

Hardware proficiency:

VLSI, Digital design, Digital Communication.

Domain Knowledge: SONET/ SDH, CAN.
INTERESTS:   

Ř  VLSI (ASIC and FPGA)
Ř
  Embedded Systems
Ř Electronic Communication
Ř  System Software
Ř 
Web designing
Ř 
Digital Signal Processing  

 

PROJECTS UNDERTAKEN

1. ACADEMIC PROJECT

 

TEAM SIZE:4

ROLE :

Responsible for designing and implementing atoms module, which includes identifying atoms for every atom and identifying the surface atoms by finding the hydrophilic atoms.

TITLE: “Molecular Docking Applications

PROJECT PROFILE:

Molecular docking System is a Standalone Embedded application. This application helps the chemical scientists in fetching the samples of different atoms and studies the molecular structures of atoms.

The binding site and the bound conformation of the two molecules are to be calculated. Development of docking techniques involved two stages:

·         Identify Surface Representation: efficiently represent the docking surface and regions of interests.

·        Surface Matching: match corresponding surfaces to optimize binding store.

 

 2. ACADEMIC PROJECT

 

 

TEAM SIZE:1

TITLE: WAP Based E-Mail Gateway  ”  

PROJECT PROFILE:

Email accesses from mobile phones are enabled by this project. It acts as a gateway to connect mailing access from any WAP device. Particularly mobile phones use them in large scale. Designed a mobile shaped interface using WML and back-end using Servlets.

·         Maintain a detailed list of all the users with their personal details like address, phone numbers etc.

·         Add a new user to the list, option to change an existing users password.

·         This gives access to checking mails, sending and receiving mails from mobile itself.

·         Option of a user signing up.

·         Maintain a database where u can store many kinds of pictures, which will be used by the user to send any picture messages.

3. Sonet/SDH Verification

 

 

 


Development SONET/SDH SystemVerilog Verification IP
 

Currently working on development of verification environment for SONET/SDH SV-IP. Task includes developing SONET/SDH SV-IP, which is used in the environment as reference SONET/SDH model, data & Temporal checkers, scoreboard and monitors.
The SV-IP, checkers, scoreboard and monitors are developed using ‘System Verilog’

• SONET/SDH SV-IP – Models the general SONET/SDH device specification   by the GR253CORE.003.

• Monitor – It acts as a SONET/SDH passive node (Receiver) in system.

• Output checkers – These are re-active checkers. Whenever any output changes, these checkers will be triggered.

Scoreboard – Main test model which checks for the correct transmission/reception of messages and the procedures involved.
 

4.Can Protocol Verification
 
Implementation of verification environment for CAN Protocol

 

Developed a verification environment for CAN protocol using SystemVerilog. Verification component is composed by a configurable number of CAN agents, able to generate and inject frames or respond to frame requests according to CAN specification. It includes a monitor that logs all traffic information and collects items for test functional coverage. The embedded protocol checker is a runtime tool checking CAN rules of the current bus traffic and the checker prompts the user about the errors.

Responsible for implementation of Scoreboard.

• Main test model which checks for the correct transmission / reception of messages and the procedures involved.

 

ACTIVITIES with INTERNET

 

Being a part of the website http://electrosofts.com, I have written the following technical articles:

·         System Verilog programming article “System Verilog

·          System Verilog Tutorial

 

PERSONAL PROFILE

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Name                      : ABHIRAM RAO
Father’s Name        : DR.D.SHRIPATHI RAO
Date of Birth           : 22-10-1983
Nationality              : Indian
Religion                   : Hindu
Mother Tongue       : Tulu
Sex                         : Male
Marital Status         : Single
Languages Known  : English, Kannada, Hindi            

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